Display controllers of computers must access screen memory, reading and writing data that is to be displayed. Typically, to save address space, the memory is accessed in a page mode, whereby a page of data is read or written in a block, from or to consecutive memory addresses defined by a base address. These memory addresses are defined by an aperture.
An aperture is an address space which maps to a memory, so that a host central processing unit (CPU) may read or write that memory directly. A memory supporting a VGA display has several possible aperture configurations, e.g. 32K bytes beginning at a memory segment address 0xB000, 32K at 0xB800, 64K at 0xA000 or 128K at 0xA000. The configuration depends on the graphics mode used.
Many graphics modes that are used in modern computers are retained for historical reasons, i.e. for compatibility with older computers, and emulate older display adapters such as CGA or MDA display adapters. For this reason modern computers have many aperture configurations.
There are currently five standard host expansion buses for microprocessors having type x86 CPUs: ISA (Industry Standard Architecture), EISA (Extended ISA), MCA (MicroChannel Architecture), VLB (VESA Local Bus), and PCI (Peripheral Component Interconnect). The largest number of personal computers in current use contain ISA buses, which support addressing of up to only 16 Mb. As will be described below, a computer using this type of bus also is limited in the size of aperture it can use.
As shown in FIG. 1, which illustrates a prior art memory architecture, VGA operated in so-called planar mode. This memory used four planes 1 of 64 Kbytes, which were each accessed using the same address space. Any of the planes could be masked out. This allowed the entire 256K VGA screen memory to be accessed through a 64K address space.
In more recent years, display adapters have been designed with increasing amounts of memory, to handle higher resolution and deeper pixel depths, for example 512K, 1M, 2M, or even likely up to 8M. To solve the problem of addressability, programmers began to page the aperture, ceasing use of planar modes because they were difficult to use, and they no longer needed them for full memory addressability. Read pages and write pages were specified independently, avoiding the use of intermediate buffers.
To access screen memory in more recent display adapters, with reference to FIG. 2, assume that a blit (transfer of image data from one part of the screen memory 3 to another) operation is to be performed, a common operation. The host CPU sets read and write pages 5 and 7 independently, setting independent apertures for read and write. It reads the memory page 5 using the read aperture and then directly writes the memory page 7 using the write aperture, in a memory move operation. Without independent read and write pages, the host CPU must set the source page, read using the aperture into a host buffer, set the destination page, and write to the aperture from the host buffer. These read and write pages may be mapped to the same address space.
In the independently set read and write procedure noted above, a problem occurs when one or both of the pages crosses a page boundary 9, as shown in FIG. 3. Pages tended to be either 64K or 128K in size and could only be set with boundaries which were a multiple of 64K or 128K respectively. For example, the read page 5 in FIG. 3 is so large that it crosses the boundary 9 in the memory 3 which boundary is set by the aperture. The aperture is dependent on the type of host bus.
In a worst case scenario, both read and write pages cross a page boundary, causing three page changes (or more page changes if either source or destination are greater in size than a maximum page size. In the best case scenario, both source and destination pages are less than the page size in length, and do not cross any page boundaries, and result in only one page change in a read and write (move) operation described above. It will be understood that each page change results in a performance penalty.
Linear apertures were introduced with the introduction of the 80386 CPU. In this type of aperture, sizes greater than or equal to the memory size can be specified, and the aperture can be configured to any base memory address location. On CPUs of the x86 family earlier than the 80386, screen memory only up to 16M could be addressed, and large linear apertures would constrain the maximum system memory size. However at this time the 80386 and later CPUs of this family can address up to 4G of memory, and therefore a multi-megabyte aperture can be used with virtually no penalty. A variable page boundary 11 is shown in FIG. 4, to illustrate this concept.
Yet both applications and display adapters should be able to be used on the older ISA bus architecture, as well as the newer 80386 and higher CPU architectures. To revert to the paged aperture scheme for the 80386 CPU in order to provide backward compatibility inflicts a heavy performance penalty for paging.
Thus until now, either the performance penalty must be accepted, or backward compatibility of the display adapter unavailable.